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? semiconductor components industries, llc, 2001 april, 2001 rev. 1 1 publication order number: mc74lvx259/d mc74lvx259 8-bit addressable latch/1-of-8 decoder cmos logic level shifter with lsttlcompatible inputs the mc74lvx259 is an 8bit addressable latch fabricated with silicon gate cmos technology. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the lvx259 is designed for general purpose storage applications in digital systems. the device has four modes of operation as shown in the mode selection table.. in the addressable latch mode, the data on data in is written into the addressed latch. the addressed latch follows the data input with all nonaddressed latches remaining in their previous states. in the memory mode, all latches remain in their previous state and are unaffected by the data or address inputs. in the oneofeight decoding or demultiplexing mode, the addressed output follows the state of data in with all other outputs in the low state. in the reset mode, all outputs are low and unaffected by the address and data inputs. when operating the lvx259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. therefore, this should only be done while in the memory mode. the mc74lvx259 input structure provides protection when voltages up to 7 v are applied, regardless of the supply voltage. this allows the mc74lvx259 to be used to interface 5 v circuits to 3 v circuits. ? high speed: t pd = 7.0 ns (typ) at v cc = 3.3 v ? low power dissipation: i cc = 2 m a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? cmoscompatible outputs: v oh > 0.8 v cc ; v ol < 0.1 v cc @load ? power down protection provided on inputs and outputs ? balanced propagation delays ? pin and function compatible with other standard logic families ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; machine model > 200 v http://onsemi.com ordering information soic16 d suffix case 751b tssop16 dt suffix case 948f soic eiaj16 m suffix case 966 marking diagrams lvx259 awlyyww lvx 259 awlyww lvx259 alyw device package shipping mc74lvx259d so16 48 units/rail mc74lvx259dr2 so16 2500 units/reel mc74lvx259dt tssop16 96 units/rail tssop16 2000 units/reel mc74lvx259m so eiaj16 48 units/rail mc74lvx259mel so eiaj16 2000 units/reel mc74lvx259dtr2 a = assembly location wl or l = wafer lot yy or y = year ww or w = work week 1 8 9 16 1 8 16 9 1 16 9 8
mc74lvx259 http://onsemi.com 2 q7 4 3 2 1 a0 a1 a2 noninverting outputs address inputs figure 1. pin assignment data in 13 15 14 reset enable 5 6 7 9 10 11 12 q6 q5 q4 q3 q2 q1 q0 pin 16 = v cc pin 8 = gnd mode selection table latch selection table 4 figure 2. logic diagram 5 6 7 8 10 11 12 15 14 13 3 2 1 a0 a1 a2 2 1 4 bin/oct 1 0 2 4 3 5 6 7 en a0 a1 a2 0 2 dmux 1 0 2 4 3 5 6 7 g 0 7 id r q7 q6 q5 q4 q3 q2 q1 q0 15 14 13 3 2 1 en id r 4 5 6 7 8 10 11 12 q7 q6 q5 q4 q3 q2 q1 q0 enable reset mode l h l hl h l h addressable latch memory 8line demultiplexer reset address inputs latch addressed l h l h h l h cb a l l h h l l h h l l h h l h l h l q0 q1 q2 q3 q4 q5 q6 q7 figure 3. iec logic symbol 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 a0 a2 a1 gnd data in enable reset v cc q0 q1 q3 q2 q7 q6 q5 q4
mc74lvx259 http://onsemi.com 3 d figure 4. expanded logic diagram data input 13 4 q0 d 5 q1 d 6 q2 d 7 q3 d 9 q4 d 10 q5 d 11 q6 d 12 q7 3 to 8 decoder enable 14 reset 15 a0 a1 a2 address inputs
mc74lvx259 http://onsemi.com 4 maximum ratings (note 1.) symbol parameter value unit v cc positive dc supply voltage 0.5 to +7.0 v v in digital input voltage 0.5 to +7.0 v v out dc output voltage 0.5 to v cc +0.5 v i ik input diode current 20 ma i ok output diode current 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air soic package tssop 200 180 mw t stg storage temperature range 65 to +150 c v esd esd withstand voltage human body model (note 2.) machine model (note 3.) charged device model (note 4.) >2000 >200 >2000 v i latchup latchup performance above v cc and below gnd at 125 c (note 5.) 300 ma ja thermal resistance, junction to ambient soic package tssop 143 164 c/w 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e recommended operating conditions. 2. tested to eia/jesd22a114a 3. tested to eia/jesd22a115a 4. tested to jesd22c101a 5. tested to eia/jesd78 recommended operating conditions symbol characteristics min max unit v cc dc supply voltage 2.0 3.6 v v in dc input voltage 0 5.5 v v out dc output voltage 0 v cc v t a operating temperature range, all package types 40 85 c t r , t f input rise or fall time v cc = 3.3 v + 0.3 v 0 100 ns/v
mc74lvx259 http://onsemi.com 5 dc characteristics (voltages referenced to gnd) v cc t a = 25 c 40 c t a 85 c symbol parameter condition (v) min typ max min max unit v ih minimum highlevel input voltage 2.0 3.0 3.6 0.75 v cc 0.7 v cc 0.7 v cc 0.75 v cc 0.7 v cc 0.7 v cc v v il maximum lowlevel input voltage 2.0 3.0 3.6 0.25 v cc 0.3 v cc 0.3 v cc 0.25 v cc 0.3 v cc 0.3 v cc v v oh highlevel output vlt i oh = 50 m a 2.0 1.9 2.0 1.9 v oh g voltage i oh = 50 m a 3.0 2.9 3.0 2.9 i oh = 4 ma 3.0 2.58 2.48 v ol lowlevel output vlt i ol = 50 m a 2.0 0.0 0.1 0.1 v ol voltage i ol = 50 m a 3.0 0.0 0.1 0.1 i ol = 4 ma 3.0 0.36 0.44 i in input leakage current v in = 5.5 v or gnd 0 to 3.6 0.1 1.0 m a i cc maximum quiescent supply current (per package) v in = v cc or gnd 3.6 1.0 1.0 2.0 m a ????????????????????????????????? ????????????????????????????????? ac electrical characteristics input t r = t f = 3.0 ns ???? ???? ????????? ????????? ????????? ????????? ???????? ???????? t a = 25 c ?????? ?????? 40 c t a 85 c ?? ?? ???? ???? symbol ????????? ????????? parameter ????????? ????????? test conditions ??? ??? min ???? ???? typ ??? ??? max ??? ??? min ???? ???? max ?? ?? unit ???? ? ?? ? ???? t plh , t phl ????????? ? ??????? ? ????????? maximum propagation delay, data to output (figures 5 and 9) ????????? ? ??????? ? ????????? v cc = 2.7 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 6.3 9.0 ??? ? ? ? ??? 9.0 14.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 12.0 15.0 ?? ?? ?? ns ???? ? ?? ? ???? ????????? ? ??????? ? ????????? (figures 5 and 9) ????????? ? ??????? ? ????????? v cc = 3.3 v 0.3 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 5.6 8.0 ??? ? ? ? ??? 8.0 12.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 11.0 14.0 ?? ?? ?? ???? ? ?? ? ???? t plh , t phl ????????? ? ??????? ? ????????? maximum propagation delay, address select to output (figures 6 and 9) ????????? ? ??????? ? ????????? v cc = 2.7 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 6.3 9.0 ??? ? ? ? ??? 9.0 14.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 12.0 15.0 ?? ?? ?? ns ???? ? ?? ? ???? ????????? ? ??????? ? ????????? (figures 6 and 9) ????????? ? ??????? ? ????????? v cc = 3.3 v 0.3 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 5.6 8.0 ??? ? ? ? ??? 8.0 12.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 11.0 14.0 ?? ?? ?? ???? ? ?? ? ???? t plh , t phl ????????? ? ??????? ? ????????? maximum propagation delay, enable to output (figures no tag and 9) ????????? ? ??????? ? ????????? v cc = 2.7 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 6.3 9.0 ??? ? ? ? ??? 9.0 14.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 12.0 15.0 ?? ?? ?? ns ???? ???? ????????? ????????? (figures no tag and 9) ????????? ????????? v cc = 3.3 v 0.3 v c l = 15pf c l = 50pf ??? ??? ???? ???? 5.6 8.0 ??? ??? 9.0 12.0 ??? ??? 1.0 1.0 ???? ???? 11.0 14.0 ?? ?? ???? ? ?? ? ???? t phl ????????? ? ??????? ? ????????? maximum propogation delay, reset to output (figures 7 and 9) ????????? ? ??????? ? ????????? v cc = 2.7 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 6.3 9.0 ??? ? ? ? ??? 9.0 14.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 12.0 15.0 ?? ?? ?? ns ???? ? ?? ? ???? ????????? ? ??????? ? ????????? (figures 7 and 9) ????????? ? ??????? ? ????????? v cc = 3.3 v 0.3 v c l = 15pf c l = 50pf ??? ? ? ? ??? ???? ? ?? ? ???? 5.6 8.0 ??? ? ? ? ??? 9.0 12.0 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 11.0 14.0 ?? ?? ?? ???? ???? c in ????????? ????????? maximum input capacitance ????????? ????????? ??? ??? ???? ???? 6 ??? ??? 10 ??? ??? ???? ???? 10 ?? ?? pf typical @ 25 c, v cc = 3.3 v c pd power dissipation capacitance (note 6.) 30 pf 6. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc . c pd is used to determine the noload dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc .
mc74lvx259 http://onsemi.com 6 timing requirements input t r = t f = 3.0 ns ???? ???? ?????????? ?????????? ????????? ????????? ??????? ??????? t a = 25 c ????? ????? t a = 85 c ??? ??? ???? ???? symbol ?????????? ?????????? parameter ????????? ????????? test conditions ??? ??? min ??? ??? typ ??? ??? max ??? ??? min ??? ??? max ??? ??? unit ???? ???? t w ?????????? ?????????? minimum pulse width, reset or enable ????????? ????????? v cc = 2.7 v ??? ??? 4.5 ??? ??? ??? ??? ??? ??? 5.0 ??? ??? ??? ??? ns ???? ???? ?????????? ?????????? reset or enable (figure 8) ????????? ????????? v cc = 3.3 v 0.3 v ??? ??? 4.5 ??? ??? ??? ??? ??? ??? 5.0 ??? ??? ??? ??? ???? ???? t su ?????????? ?????????? minimum setup time, address or data to enable ????????? ????????? v cc = 2.7 v ??? ??? 4.0 ??? ??? ??? ??? ??? ??? 4.0 ??? ??? ??? ??? ns ???? ???? ?????????? ?????????? address or data to enable (figure 8) ????????? ????????? v cc = 3.3 v 0.3 v ??? ??? 3.0 ??? ??? ??? ??? ??? ??? 3.0 ??? ??? ??? ??? ???? ???? t h ?????????? ?????????? minimum hold time, enable to address or data ????????? ????????? v cc = 2.7 v ??? ??? 2.0 ??? ??? ??? ??? ??? ??? 2.0 ??? ??? ??? ??? ns ???? ? ?? ? ???? ?????????? ? ???????? ? ?????????? enable to address or data (figure 7 or 8) ????????? ? ??????? ? ????????? v cc = 3.3 v 0.3 v ??? ? ? ? ??? 2.0 ??? ? ? ? ??? ??? ? ? ? ??? ??? ? ? ? ??? 2.0 ??? ? ? ? ??? ??? ? ? ? ??? ???? ???? t r, t f ?????????? ?????????? maximum input, rise and fall times ????????? ????????? v cc = 2.7 v ??? ??? ??? ??? ??? ??? 400 ??? ??? ??? ??? 300 ??? ??? ns ???? ???? ?????????? ?????????? rise and fall times (figure 5) ????????? ????????? v cc = 3.3 v 0.3 v ??? ??? ??? ??? ??? ??? 300 ??? ??? ??? ??? 300 ??? ??? *includes all probe and jig capacitance figure 5. switching waveform c l * test point device under test output output q data in 50% t plh t phl t f gnd v cc 50% figure 6. switching waveform t r 50% 50% t phl 50% t phl data in address select output q v cc gnd v cc gnd v cc gnd figure 7. switching waveform figure 8. switching waveform figure 9. switching waveform 50% t w 50% t phl data in output q reset v cc gnd v cc gnd v cc gnd v cc gn d data in output q enable data in or address select enable v cc gnd v cc gnd t w t w 50% 50% 50% t phl t phl 50% 50% t su t h(h) t h(h) t su figure 10. test circuit
mc74lvx259 http://onsemi.com 7 d 1 for components 10 pitches cumulative tolerance on tape 0.2 mm ( 0.008o) 2.0 mm 1.2 mm and larger center lines of cavity embossment user direction of feed k 0 see note 7. p 0 p 2 d e f w b 0 + + + k t b 1 top cover tape p see note 7. a 0 for machine reference only including draft and radii concentric around b 0 r min. tape and components shall pass around radius aro without damage bending radius *top cover tape thickness (t 1 ) 0.10 mm (0.004o) max. embossed carrier embossment typical component cavity center line typical component center line maximum component rotation 10 camber (top view) allowable camber to be 1 mm/100 mm nonaccumulative over 250 mm 100 mm (3.937o) 1 mm (0.039o) max 250 mm (9.843o) 1 mm max tape 7. a 0 , b 0 , and k 0 are determined by component size. the clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. the component cannot rotate more than 10 within the determined cavity figure 11. carrier tape specifications
mc74lvx259 http://onsemi.com 8 embossed carrier dimensions (see notes 8. and 9.) tape size b 1 max d d 1 e f k p p 0 p 2 r t w 8 mm 4.35 mm (0.179o) 1.5 mm + 0.1 0.0 (0.059o 0 004 1.0 mm min (0.179o) 1.75 mm 0.1 (0.069 0.004o) 3.5 mm 0.5 (1.38 0.002o) 2.4 mm max (0.094o) 4.0 mm 0.10 (0.157 0.004o) 4.0 mm 0.1 (0.157 0.004o) 2.0 mm 0.1 (0.079 0.004o) 25 mm (0.98o) 0.6 mm (0.024) 8.3 mm (0.327) 12 mm 8.2 mm (0.323o) ( +0.004 0.0) 1.5 mm min (0.060) ) 5.5 mm 0.5 (0.217 0.002o) 6.4 mm max (0.252o) 4.0 mm 0.10 (0.157 0.004o) 8.0 mm 0.10 (0.315 0.004o) ) ) 30 mm (1.18o) 12.0 mm 0.3 (0.470 0.012o) 16 mm 12.1 mm (0.476o) 7.5 mm 0.10 (0.295 0.004o) 7.9 mm max (0.311o) 4.0 mm 0.10 (0.157 0.004o) 8.0 mm 0.10 (0.315 0.004o) 12.0 mm 0.10 (0.472 0.004o) 16.3 mm (0.642) 24 mm 20.1 mm (0.791o) 11.5 mm 0.10 (0.453 0.004o) 11.9 mm max (0.468o) 16.0 mm 0.10 (0.63 0.004o) 24.3 mm (0.957) 8. metric dimensions governenglish are in parentheses for reference only. 9. a 0 , b 0 , and k 0 are determined by component size. the clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. the component cannot rotate more than 10 within the determined cavity
mc74lvx259 http://onsemi.com 9 13.0 mm 0.2 mm (0.512o 0.008o) 1.5 mm min (0.06o) 50 mm min (1.969o) 20.2 mm min (0.795o) full radius t max g a figure 12. reel dimensions reel dimensions tape size t&r suffix a max g t max 8 mm t1, t2 178 mm (7o) 8.4 mm, +1.5 mm, 0.0 (0.33o + 0.059o, 0.00) 14.4 mm (0.56o) 8 mm t3, t4 330 mm (13o) 8.4 mm, +1.5 mm, 0.0 (0.33o + 0.059o, 0.00) 14.4 mm (0.56o) 12 mm r2 330 mm (13o) 12.4 mm, +2.0 mm, 0.0 (0.49o + 0.079o, 0.00) 18.4 mm (0.72o) 16 mm r2 360 mm (14.173o) 16.4 mm, +2.0 mm, 0.0 (0.646o + 0.078o, 0.00) 22.4 mm (0.882o) 24 mm r2 360 mm (14.173o) 24.4 mm, +2.0 mm, 0.0 (0.961o + 0.078o, 0.00) 30.4 mm (1.197o) direction of feed barcode label hole pocket figure 13. reel winding direction
mc74lvx259 http://onsemi.com 10 tape trailer (connected to reel hub) no components 160 mm min tape leader no components 400 mm min components direction of feed cavity tape top tape figure 14. tape ends for finished goods figure 15. tssop and soic r2 reel configuration/orientation user direction of feed tape utilization by package tape size soic tssop qfn sc88a / sot353 sc88/sot363 8 mm 5, 6lead 12 mm 8lead 8, 14, 16lead 8, 14, 16lead 16 mm 14, 16lead 20, 24lead 20, 24lead 24 mm 18, 20, 24, 28lead 48, 56lead 48, 56lead
mc74lvx259 http://onsemi.com 11 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 soic16 d suffix case 751b05 issue j ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n tssop16 dt suffix case 948f01 issue o
mc74lvx259 http://onsemi.com 12 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soic eiaj16 m suffix case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74lvx259/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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